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freescale semiconductor, inc. reserves t he right to change the detail specifications, as may be required, to permit improvements in the design of its products. document number: mc33984 rev. 14.0, 5/2012 freescale semiconductor technical data ? freescale semiconductor, inc. , 2007-2012. all rights reserved. dual intelligent high-current self-protected silicon high side switch (4.0 m ohm ) the 33984 is a dual self-protected 4.0 m silicon switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. the 33984 is designed for harsh environments, and it includes self -recovery features. the device is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads. programming, control and diagnostics are implemented via the serial peripheral interface (spi). a dedicated parallel input is available for alternate and pulse-width mo dulation (pwm) control of each output. spi-programmable fault trip thresholds allow the device to be adjusted for optimal performance in the application. the 33984 is packaged in a power-enhanced 12 x 12 mm nonleaded pqfn package with exposed tabs. features ? dual 4.0 m max high side switch with parallel input or spi control ? 6.0 v to 27 v operating voltage with standby currents < 5.0 a ? output current monitoring with two spi-selectable current ratios ? spi control of over-current limit, over-current fault blanking time, output off open load detection, output on/off control, watchdog timeout, slew-rates, and fault status reporting ? spi status reporting of over-curr ent, open and shorted loads, over- temperature, under-voltage and ov er-voltage shutdown, fail-safe pin status, and program status ? enhanced -16 v reverse polarity v pwr protection figure 1. 33984 simplified application diagram high side switch 33984 ordering information device (add r2 suffix for tape and reel ) temperature range (t a ) package MC33984CHFK - 40 c to 125 c 16 pqfn bottom view fk suffix 98arl10521d 16-pin pqfn vdd i/o i/o so sclk cs si i/o i/o i/o a/d vpwr fs wake si sclk cs so rst ino in1 csns fsi gnd hs1 hs0 gnd load load 33984 mcu v dd v dd v dd v pwr
analog integrated circuit device data 2 freescale semiconductor 33984 device variation device variation table 1. device variation freescale part no. output clamp energy reference location od3 bit for x111 address reference location mc33984c 0.5j table 3 1 table 16
analog integrated circuit device data freescale semiconductor 3 33984 internal block diagram internal block diagram figure 2. 33984 simplifi ed internal block diagram gnd programmable watchdog 310?2500 ms over-temperature detection selectable output current recopy 1/20500 or 1/41000 open load detection logic selectable over- blanking time 0.15?155 ms selectable over-current 7.5 ?25 a selectable over-current 100a or 75a internal regulator programmable switch delay 0 ?525 ms selectable slew rate gate drive over-voltage protection hs0 csns vpwr vdd fsi hs1 hs0 hs1 high detection low detection spi 3.0 mhz cs so si sclk fs in[0:1] rst wake i dwn r dwn i up i up v ic v ic current low detection
analog integrated circuit device data 4 freescale semiconductor 33984 pin connections pin connections figure 3. 33984 pin connections (transparent top view) table 2. pin definitions functional descriptions of many of thes e pins can be found in the functional pin description section beginning on page 17 . pin pin name pin function formal name definition 1 csns output output current monitoring this pin is used to output a current proportional to the designated hs0-1 output. 2 wake input wake this pin is used to input a logic [1] signal so as to enable the watchdog timer function. 3 rst input reset (active low) this input pin is used to initiali ze the device configuration and fault registers, as well as place the device in a low current sleep mode. 4 in0 input direct input 0 this input pin is used to directly control the output hs0. 5 fs output fault status (active low) this is an open drain configured out put requiring an external pull-up resistor to vdd for fault reporting. 6 fsi input fail-safe input the value of the resistance connected between this pin and ground determines the state of the outputs after a watchdog timeout occurs. 7 cs input chip select (active low) this input pin is connected to a chip select output of a master microcontroller (mcu). 8 sclk input serial clock this input pin is connected to the mcu providing the required bit shift clock for spi communication. 9 si input serial input this is a command data input pin connected to the spi serial data output of the mcu or to the so pin of the previous device of a daisy chain of devices. 10 vdd input digital drain voltage (power) this is an external voltage input pi n used to supply power to the spi circuit. hs1 hs0 16 15 vpwr 14 gnd 13 csns in0 fs fsi cs sclk rst wake si vdd so in1 1 11 10 9 8 7 6 5 4 3 2 12 transparent top view
analog integrated circuit device data freescale semiconductor 5 33984 pin connections 11 so output serial output this output pin is connected to the spi serial data input pin of the mcu or to the si pin of the next device of a daisy chain of devices. 12 in1 input direct input 1 this input pin is used to directly control the output hs1. 13 gnd ground ground this pin is the ground for the logi c and analog circuitry of the device. 14 vpwr input positive power supply this pin connects to the positive pow er supply and is the source input of operational power for the device. 15 hs1 output high side output 1 protected 4.0 m high side power output to the load. 16 hs0 output high side output 0 protected 4.0 m high side power output to the load. table 2. pin definitions (continued) functional descriptions of many of thes e pins can be found in the functional pin description section beginning on page 17 . pin pin name pin function formal name definition
analog integrated circuit device data 6 freescale semiconductor 33984 electrical characteristics maximum ratings electrical characteristics maximum ratings table 3. maximum ratings all voltages are with respect to ground unless otherwise noted. rating symbol value unit electrical ratings operating voltage range steady-state v pwr -16 to 41 v vdd supply voltage v dd -0.3 to 5.5 v input/output voltage (1) v in[0:1] , rst , fsi csns, si, sclk, cs , fs - 0.3 to 7.0 v so output voltage (1) v so - 0.3 to v dd + 0.3 v wake input clamp current i cl(wake) 2.5 ma csns input clamp current i cl(csns) 10 ma output voltage positive negative v hs 41 -15 v output current (2) i hs[0:1] 30 a output clamp energy (3) 33984b 33984c e cl[0:1] 0.75 0.5 j esd voltage (4) human body model (hbm) charge device model (cdm) corner pins (1, 12, 15, 16) all other pins (2, 11, 13, 14) v esd1 v esd3 2000 750 500 v notes 1. exceeding this voltage limit may c ause permanent damage to the device. 2. continuous high side output current rating so long as maximum junction temperature is not exceeded. calculation of maximum ou tput current using package therma l resistance is required. 3. active clamp energy using single-pulse method (l = 16 mh, r l = 0,v pwr = 12 v, t j = 150c). 4. esd1 testing is performed in accordance with the human body model (hbm) (c zap = 100 pf, r zap = 1500 ); esd3 testing is performed in accordance with the charge de vice model (cdm), robotic (czap = 4.0 pf).
analog integrated circuit device data freescale semiconductor 7 33984 electrical characteristics maximum ratings thermal ratings operating temperature ambient junction t a t j - 40 to 125 - 40 to 150 c storage temperature t stg - 55 to 150 c thermal resistance (5) junction-to-case junction-to-ambient r jc r ja <1.0 30 c/w peak package reflow temperature during reflow (6) , (7) t pprt note 7 c notes 5. device mounted on a 2s2p test board according to jedec jesd51-2. 6. pin soldering temperature limit is for 40 seconds maximum duration. not designed fo r immersion soldering. exceeding these lim its may cause malfunction or permanent damage to the device. 7. freescale?s package reflow capability meets pb-free requirem ents for jedec standard j-std-020. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.frees cale.com, search by part number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts. (i .e. mc33xxxd enter 33xxx), and review parametrics. table 3. maximum ratings all voltages are with respect to ground unless otherwise noted. rating symbol value unit
analog integrated circuit device data 8 freescale semiconductor 33984 electrical characteristics static electrical characteristics static electrical characteristics table 4. static electric al characteristics characteristics noted under conditions 4.5 v v dd 5.5 v, 6.0 v v pwr 27 v, -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions , unless otherwise noted. characteristic symbol min typ max unit power input battery supply voltage range full operational v pwr 6.0 ? 27 v v pwr operating supply current output on, i hs0 and i hs1 = 0 a i pwr(on) ? ? 20 ma v pwr supply current output off, open load detection disabled, wake > 0.7 x v dd , rst = v logic high i pwr(sby) ? ? 5.0 ma sleep state supply current (v pwr < 14 v, rst < 0.5 v, wake < 0.5 v) t j = 25 c t j = 85 c i pwr(sleep) ? ? ? ? 10 50 a vdd supply voltage v dd(on) 4.5 5.0 5.5 v vdd supply current no spi communication 3.0 mhz spi communication i dd(on) ? ? ? ? 1.0 5.0 ma vdd sleep state current i dd(sleep) ? ? 5.0 a over-voltage shutdown threshold v pwr(ov) 28 32 36 v over-voltage shutdown hysteresis v pwr(ovhys) 0.2 0.8 1.5 v under-voltage output shutdown threshold (8) v pwr(uv) 5.0 5.5 6.0 v under-voltage hysteresis (9) v pwr(uvhys) ? 0.25 ? v under-voltage power-on reset v pwr(uvpor) ? ? 5.0 v notes 8. this applies to all intern al device logic supplied by v pwr and assumes the external v dd supply is within specification. 9. this applies when the under-voltage fault is not latched (in[0 : 1] = 0).
analog integrated circuit device data freescale semiconductor 9 33984 electrical characteristics static electrical characteristics power output output drain-to-source on resistance ( i hs[0:1] = 15 a, t j = 25 c) v pwr = 6.0 v v pwr = 10 v v pwr = 13 v r ds(on) ? ? ? ? ? ? 6.0 4.0 4.0 m output drain-to-source on resistance (i hs[0:1] = 15 a, t j = 150 c) v pwr = 6.0 v v pwr = 10 v v pwr = 13 v r ds(on) ? ? ? ? ? ? 10.2 6.8 6.8 m output source-to-drain on resistance i hs[0:1] = 15 a, t j = 25 c (10) v pwr = -12 v r ds(on) ? ? 8.0 m output over-current high detection levels (9.0 v < v pwr < 16 v) soch = 0 soch = 1 i och0 i och1 80 60 100 75 120 90 a over-current low detect ion levels (socl[2:0]) 000 001 010 011 100 101 110 111 i ocl0 i ocl1 i ocl2 i ocl3 i ocl4 i ocl5 i ocl6 i ocl7 21 18 16 14 12 10 8.0 6.0 25 22.5 20 17.5 15 12.5 10 7.5 29 27 24 21 18 15 12 9.0 a current sense ratio (9.0 v < v pwr < 16 v, csns < 4.5 v) dicr d2 = 0 dicr d2 = 1 c sr0 c sr1 ? ? 1/20500 1/41000 ? ? ? current sense ratio (c sr0 ) accuracy output current 5.0 a 10 a 12.5 a 15 a 20 a 25 a c sr0_acc - 20 -14 -13 -12 -13 -13 ? ? ? ? ? ? 20 14 13 12 13 13 % notes 10. source-drain on resistance (reverse drain-to -source on resistance) with negative polarity v pwr . table 4. static electrical characteristics (continued) characteristics noted under conditions 4.5 v v dd 5.5 v, 6.0 v v pwr 27 v, -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions , unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 10 freescale semiconductor 33984 electrical characteristics static electrical characteristics power output (continued) current sense ratio (c sr1 ) accuracy output current 5.0 a 10 a 12.5 a 15 a 20 a 25 a c sr1_acc - 25 -19 -18 -17 -18 -18 ? ? ? ? ? ? 25 19 18 17 18 18 % current sense clamp voltage csns open; i hs[0:1] = 29 a v cl(csns) 4.5 6.0 7.0 v open load detection current (11) i oldc 30 ? 100 a output fault detection threshold output programmed off v old(thres) 2.0 3.0 4.0 v output negative clamp voltage 0.5 a < i hs[0:1] < 2.0 a, output off v cl - 20 ? -15 v over-temperature shutdown (12) t sd 160 175 190 c over-temperature shutdown hysteresis (12) t sd(hys) 5.0 ? 20 c notes 11. output off open load detection current is the current requir ed to flow through the load for the purpose of detecting the exi stence of an open load condition when the spec ific output is commanded off. 12. guaranteed by process monitoring. not production tested. table 4. static electrical characteristics (continued) characteristics noted under conditions 4.5 v v dd 5.5 v, 6.0 v v pwr 27 v, -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions , unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 11 33984 electrical characteristics static electrical characteristics control interface input logic high voltage (13) v ih 0.7 x v dd ? ? v input logic low voltage (13) v il ? ? 0.2 x v dd v input logic voltage hysteresis (14) v in[0:1] (hys) 100 600 1200 mv input logic pull-down current (sclk, in, si) i dwn 5.0 ? 20 a rst input voltage range v rst 4.5 5.0 5.5 v so, fs tri-state capacitance (15) c so ? ? 20 pf input logic pull-down resistor ( rst ) and wake r dwn 100 200 400 k input capacitance (15) c in ? 4.0 12 pf wake input clamp voltage (16) i cl(wake) < 2.5 ma v cl(wake) 7.0 ? 14 v wake input forward voltage i cl(wake) = - 2.5 ma v f(wake) - 2.0 ? - 0.3 v so high-state output voltage i oh = 1.0 ma v soh 0.8 x v dd ? ? v fs , so low-state output voltage i ol = -1.6 ma v sol ? 0.2 0.4 v so tri-state leakage current cs > 0.7 v dd i so(leak) - 5.0 0 5.0 a input logic pull-up current (17) cs , v in[0:1] > 0.7 x v dd i up 5.0 ? 20 a fsi input pin external pull-down resistance fsi disabled, hs[0:1] indeterminate fsi enabled, hs[0:1] off fsi enabled, hs0 on, hs1 off fsi enabled, hs[0:1] on rfs rfsdis rfsoffoff rfsonoff rfsonon ? 6.0 15 40 0 6.5 17 infinite 1.0 7.0 19 ? k notes 13. upper and lower logic thres hold voltage range applies to si, cs , sclk, rst , in[0:1], and wake input signals. the wake and rst signals may be supplied by a derived voltage reference to v pwr . 14. no hysteresis on fsi and wake pins. parameter is guar anteed by processing monitoring but is not production tested. 15. input capacitance of si, cs , sclk, rst , and wake. this parameter is guaranteed by proc ess monitoring but is not production tested. 16. the current must be limited by a series resistance when using voltages > 7.0 v. 17. pull-up current is with cs open. cs has an active internal pull-up to v dd . table 4. static electrical characteristics (continued) characteristics noted under conditions 4.5 v v dd 5.5 v, 6.0 v v pwr 27 v, -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions , unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 12 freescale semiconductor 33984 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 5. dynamic electri cal characteristics characteristics noted under conditions 4.5 v v dd 5.5 v, 6.0 v v pwr 27 v, -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit power output timing output rising slow slew rate a (dicr d3 = 0) (18) 9.0 v < v pwr < 16 v sr ra_slow 0.2 0.6 1.2 v/ s output rising slow slew rate b (dicr d3 = 0) (19) 9.0 v < v pwr < 16 v sr rb_slow 0.03 0.1 0.3 v/ s output rising fast slew rate a (dicr d3 = 1) (18) 9.0 v < v pwr < 16 v sr ra_fast 0.4 1.0 4.0 v/ s output rising fast slew rate b (dicr d3 = 1) (19) 9.0 v < v pwr < 16 v sr rb_fast 0.03 0.1 1.2 v/ s output falling slow slew rate a (dicr d3 = 0) (18) 9.0 v < v pwr < 16 v sr fa_slow 0.2 0.6 1.2 v/ s output falling slow slew rate b (dicr d3 = 0) (19) 9.0 v < v pwr < 16 v sr fb_slow 0.03 0.1 0.3 v/ s output falling fast slew rate a (dicr d3 = 1) (18) 9.0 v < v pwr < 16 v sr fa_fast 0.8 2.0 4.0 v/ s output falling fast slew rate b (dicr d3 = 1) (19) 9.0 v < v pwr < 16 v sr fb_fast 0.1 0.35 1.2 v/ s output turn-on delay time in fast/slow slew rate (20) dicr = 0, dicr = 1 t dly(on) 1.0 15 100 s output turn-off delay time in slow slew rate mode (21) dicr = 0 t dly_slow(off) 20 230 500 s output turn-off delay time in fast slew rate mode (21) dicr = 1 t dly_fast(off) 10 60 200 s direct input switching frequency (dicr d3 = 0) f pwm ? 300 ? hz notes 18. rise and fall slew rates a measured across a 5.0 resistive load at high side output = 0.5 v to v pwr - 3.5 v. these parameters are guaranteed by process monitoring. 19. rise and fall slew rates b measured across a 5.0 resistive load at high side output = v pwr - 3.5 v to v pwr - 0.5 v. these parameters are guaranteed by process monitoring. 20. turn-on delay time measured from rising edge of in [0:1] signal that would turn the output on to v hs[0:1] = 0.5 v with r l = 5.0 resistive load. 21. turn-off delay time measured from falling edge that would turn the output off to v hs[0:1] = v pwr - 0.5 v with r l = 5.0 resistive load.
analog integrated circuit device data freescale semiconductor 13 33984 electrical characteristics dynamic electrical characteristics power output timing (continued) over-current detectio n blanking time (oclt [1:0]) 00 01 10 11 t ocl0 t ocl1 t ocl2 t ocl3 108 7.0 0.8 0.08 155 10 1.2 0.15 202 13 1.6 0.25 ms over-current high de tection blanking time t och 1.0 10 20 s cs to csns valid time (22) t cns val ? ? 10 s hs1 switching delay time (osd[2:0]) 000 001 010 011 100 101 110 111 t osd0 t osd1 t osd2 t osd3 t osd4 t osd5 t osd6 t osd7 ? 55 110 165 220 275 330 385 0 75 150 225 300 375 450 525 ? 95 190 285 380 475 570 665 ms hs0 switching delay time (osd[2:0]) 000 001 010 011 100 101 110 111 t osd0 t osd1 t osd2 t osd3 t osd4 t osd5 t osd6 t osd7 ? ? 110 110 220 220 330 330 0 0 150 150 300 300 450 450 ? ? 190 190 380 380 570 570 ms watchdog timeout (wd [1:0]) (23) 00 01 10 11 t wdto0 t wdto1 t wdto2 t wdto3 434 207 1750 875 620 310 2500 1250 806 403 3250 1625 ms notes 22. time necessary for the csns to be within 5% of the targeted value. 23. watchdog timeout delay measured from the rising edge of wake to rst from a sleep-state condition to output turn-on with the output driven off and fsi floating. the values shown ar e for wdr setting of [00]. the accuracy of t wdto is consistent for all configured watchdog timeouts. table 5. dynamic electrical characteristics (continued) characteristics noted under conditions 4.5 v v dd 5.5 v, 6.0 v v pwr 27 v, -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 14 freescale semiconductor 33984 electrical characteristics dynamic electrical characteristics spi interface characteristics recommended frequency of spi operation f spi ? ? 3.0 mhz required low state duration for rst (24) t w rst ? 50 350 ns rising edge of cs to falling edge of cs (required setup time) (25) t cs ? ? 300 ns rising edge of rst to falling edge of cs (required setup time) (25) t enbl ? ? 5.0 s falling edge of cs to rising edge of sclk (required setup time) (25) t lead ? 50 167 ns required high state duration of sclk (required setup time) (25) t wsclkh ? ? 167 ns required low state duration of sclk (required setup time) (25) t wsclkl ? ? 167 ns falling edge of sclk to rising edge of cs (required setup time) (25) t lag ? 50 167 ns si to falling edge of sclk (required setup time) (26) t si(su) ? 25 83 ns falling edge of sclk to si (required setup time) (26) t si(hold) ? 25 83 ns so rise time c l = 200 pf t rso ? 25 50 ns so fall time c l = 200 pf t fso ? 25 50 ns si, cs , sclk, incoming signal rise time (26) t rsi ? ? 50 ns si, cs , sclk, incoming signal fall time (26) t rsi ? ? 50 ns time from falling edge of cs to so low-impedance (27) t so(en) ? ? 145 ns time from rising edge of cs to so high-impedance (28) t so(dis) ? 65 145 ns time from rising edge of sclk to so data valid (29) 0.2 x v dd so 0.8 x v dd , c l = 200 pf t valid ? 65 105 ns notes 24. rst low duration measured with outputs enabled and going to off or disabled condition. 25. maximum setup time required for the 33984 is the mi nimum guaranteed time needed from the microcontroller. 26. rise and fall time of incoming si, cs , and sclk signals suggested for des ign consideration to prevent the occurrence of double pulsing. 27. time required for output status data to be available for use at so. 1.0 k on pull-up on cs . 28. time required for output status data to be terminated at so. 1.0 k on pull-up on cs . 29. time required to obtain valid data out from so following the rise of sclk. table 5. dynamic electrical characteristics (continued) characteristics noted under conditions 4.5 v v dd 5.5 v, 6.0 v v pwr 27 v, -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 15 33984 electrical characteristics timing diagrams timing diagrams figure 4. output slew rate and time delays figure 5. over-current shutdown figure 6. over-current low and high detection vpwr v pwr - 0.5v vpwr - 3v 0.5v tdly ( off) srra srrb srfa srfb cs tdly (on) v pwr v pwr -0.5 v v pwr -3.5 v 0.5 v t dly(on) sr rb_slow & sr rb_fast sr fb_slow & sr fb_fast sr fa_slow & sr fa_fast sr ra_slow & sr ra_fast t dly_slow(off) & t dly_fast(off) hs i oclx i ochx t oclx t och time load current i och0 t ocl0 t ocl1 t ocl2 t ocl3 t ochx time load current i och1 i ocl0 i ocl2 i ocl3 i ocl4 i ocl5 i ocl6 i ocl7 i ocl1
analog integrated circuit device data 16 freescale semiconductor 33984 electrical characteristics timing diagrams figure 6 illustrates the over-current detection level (ioclx, iochx) the device can reach for each over-current detection blanking time (tochx, toclx): ? during tochx, the device can reach up to ioch0 over- current level. ? during tocl3 or tocl2 or tocl1 or tocl0, the device can be programmed to detect up to iocl0. figure 7. input timing switching characteristics figure 8. sclk waveform and valid so data delay time si rstb csb sclk don?t care don?t care don?t care valid valid vih vil vih vih vih vil vil vil twrstb tlead twsclkh trsi tlag tsisu twsclkl tsi(hold) tfsi 0.7 vdd 0.2 vdd 0.7vdd 0.2vdd 0.2vdd 0.7vdd 0.7vdd tcsb tenbl rst sclk si cs 0.2 x v dd t wrst t enbl 0.2 x v dd t lead t wsclkh t rsi 0.7 x v dd 0.2 x v dd 0.7 x v dd 0.2 x v dd t si(su) t wsclkl t si(hold) t fsi 0.7 x v dd t cs t lag v ih v ih v il v il v ih v il v ih v ih so so sclk voh vol voh vol voh vol tfsi tdlylh tdlyhl t valid trso tfso 3.5v 50% trsi high-to-low 1.0v 0.7 vdd 0.2vdd 0.2 vdd 0.7 vdd low-to-high t rsi t fsi 0.7 x v dd sclk so so v oh v ol v oh v ol v oh v ol 1.0 v 0.2 x v dd 0.7 x v dd t rso t fso 0.2 x v dd t so(en) t so(dis) 3.5 v low to high high to low t valid
analog integrated circuit device data freescale semiconductor 17 33984 functional description functional pin description functional description introduction the 33984 is a dual self-protected 4.0 m silicon switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. the 33984 is designed for harsh environments, and it includes self- recovery features. the device is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads. programming, control, and diagnostics are implemented via the serial peripheral interface (spi). a dedicated parallel input is available for alternate and pulse width modulation (pwm) control of each output. spi-programmable fault trip thresholds allow the device to be adjusted for optimal performance in the application. the 33984 is packaged in a power-enhanced 12 x 12 nonleaded pqfn package with exposed tabs. functional pin description output current monitoring (csns) this pin is used to output a current proportional to the designated hs0-1 output. that current is fed into a ground- referenced resistor and its volt age is monitored by an mcu's a/d. the channel to be monitored is selected via the spi. this pin can be tri-stated through the spi. wake (wake) this pin is used to input a logic [1] signal so as to enable the watchdog timer function. an internal clamp protects this pin from high damaging volt ages when the output is current limited with an external resi stor. this input has a passive internal pull-down. reset ( rst ) this input pin is used to initialize the device configuration and fault registers, as well as place the device in a low- current sleep mode. the pin also starts the watchdog timer when transitioning from logic low to logic high. this pin should not be allowed to be logic high until v dd is in regulation. this pin has a passive internal pull-down. direct in 0 & 1 (inx) this input pin is used to directly control the output hs0 and 1. this input has an active internal pull-down current source and requires cmos logic levels. this input may be configured via the spi. fault status ( fs ) this is an open drain c onfigured output requiring an external pull-up resistor to v dd for fault reporting. when a device fault condition is detect ed, this pin is active low. specific device diagnostic faults are reported via the spi so pin. fail-safe input (fsi) the value of the resistance connected between this pin and ground determines the state of the outputs after a watchdog timeout occurs. depending on the resistance value, either all outputs are of f, on, or the output hs0 only is on. when the fsi pin is connected to gnd, the watchdog circuit and fail-safe operation are disabled. this pin incorporates an active internal pull-up current source. chip select ( cs ) this input pin is connected to a chip select output of a master microcontroller (mcu). the mcu determines which device is addressed (selected) to receive data by pulling the cs pin of the selected device logic low, enabling spi communication with the device. other unselected devices on the serial link having their cs pins pulled-up logic high disregard the spi communication data sent. this pin incorporates an active internal pull-up current source. serial clock (sclk) this input pin is connected to the mcu providing the required bit shift clock for spi communication. it transitions one time per bit transferred at an operating frequency, f spi , defined by the communication interface. the 50 percent duty cycle cmos-level serial cloc k signal is idle between command transfers. the signal is used to shift data into and out of the device. this input has an active internal pull-down current source. serial input (si) this is a command data input pin connected to the spi serial data output of the mcu or to the so pin of the previous device of a daisy c hain of devices. the input requires cmos logic-level signals and incorporates an active internal pull-down current source. device control is facilitated by the input's receiving the msb first of a serial 8-bit control command. the mcu ensures data is available upon the falling edge of sclk. the logic state of si present upon the rising edge of sclk loads that bit command into the internal command shift register. digital drain voltage (vdd) this is an external voltage input pin used to supply power to the spi circuit. in the event v dd is lost, an internal supply provides power to a portion of the logic, ensuring limited functionality of the device. all device configuration registers are reset.
analog integrated circuit device data 18 freescale semiconductor 33984 functional description functional pin description serial output (so) this output pin is connected to the spi serial data input pin of the mcu or to the si pin of the next device of a daisy chain of devices. this output will remain tri-stated (high- impedance off condition) so long as the cs pin of the device is logic high. so is only active when the cs pin of the device is asserted logic low. the generated so output signals are cmos logic levels. so output data is available on the falling edge of sclk and transitions immediately on the rising edge of sclk. positive power supply (vpwr) this pin connects to the positive power supply and is the source input of operational power for the device. the vpwr pin is a backside surface mount tab of the package. high-side output 0 & 1 (hsx) this pin protects 4.0 m high side power output to the load.
analog integrated circuit device data freescale semiconductor 19 33984 functional description functional internal block description functional internal block description power supply the 33984 is designed to operate from 4.0 to 28 v on the vpwr pin. characteristics are provided from 6.0 to 20 v for the device. the vpwr pin supplies power to internal regulator, analog , and logic circuit blocks. the v dd supply is used for serial peripheral interface (spi) communication in order to configure and diagnose the device. this ic architecture provides a low quiescent current sleep mode. applying v pwr and v dd to the device will place the device in the normal mode. the device will transit to fail-safe mode in case of failures on t he spi (watchdog timeout). high side switch: hs[0:1] those pins are the high side outputs controlling multiple automotive loads with high inrush current, as well as motors and all types of resistive and inductive loads. this n-channel mosfet with 4.0 m rds(on), is self-protected and each n-channel presents extended diagnostics in order to detect load disconnections and short-circuit fault conditions. the hs[0:1] outputs are actively clamped during a turn-off of inductive loads. mcu interface and output control in normal mode, the loads are controlled directly from the mcu through the spi. with a de dicated spi command, it is possible to independently turn on and off several loads that are pwm?d at the same frequency, and duty cycles with only one pwm signal. an analog feedback output provides a current proportional to each load current. the spi is used to configure and to read the diagnostic status (faults) of the high side output. the reported faul t conditions are: open load, short-circuit to ground (oclo-resistive and ochi-severe short-circuit), thermal shutdown, and under/over-voltage. in fail-safe mode, the loads are controlled with dedicated parallel input pins. the device is configured in default mode. mcu interface mcu interface and output control spi interface parallel control inputs power supply self-protected high side switch hs [0:1]
analog integrated circuit device data 20 freescale semiconductor 33984 functional device operation operational modes functional device operation operational modes the 33984 has four operating modes: sleep, normal, fault, and fail-safe. table 6 summarizes details contained in succeeding paragraphs. sleep mode the default mode of the 33984 is the sleep mode. this is the state of the device after first applying battery voltage (v pwr ), prior to any i/o transitions. this is also the state of the device when the wake and rst are both logic [0]. in the sleep mode, the output and all unused internal circuitry, such as the internal 5.0 v regulator, are off to minimize current draw. in addition, all spi-config urable features of the device are as if set to logic [0]. the device will transition to the normal or fail-safe operati ng modes based on the wake and rst inputs as defined in table 6 . normal mode the 33984 is in normal mode when: ?v pwr is within the normal voltage range. ? rst pin is logic [1]. ? no fault has occurred. fail-safe and watchdog if the fsi input is not gr ounded, the watchdog timeout detection is active when either the wake or rst input pin transitions from logic [0] to logic [1]. the wake input is capable of being pulled up to v pwr with a series of limiting resistance that limits the internal clamp current according to the specification. the watchdog timeout is a multiple of an internal oscillator and is specified in table 15 . as long as the wd bit (d7) of an incoming spi message is toggled within the minimum watchdog timeout period (wdto), based on the programmed value of the wdr the device will operate normally. if an internal watc hdog timeout occurs before the wd bit, the device will revert to a fail-safe mode until the device is reinitialized. during the fail-safe mode, the outputs will be on or off depending upon the resistor rfs connected to the fsi pin, regardless of the state of the va rious direct inputs and modes ( table 7 ). in this mode, the spi r egister content is retained except for over-current high and low detection levels and timing, which are reset to their default value (socl, soch, and oclt). then the watc hdog, over-voltage, over- temperature, and over-current circuitry (with default value) are fully operational. the fail-safe mode can be detected by monitoring the wdto bit d2 of the wd r egister. this bit is logic [1] when the device is in fail-safe mode. t he device can be brought out of the fail-safe mode by transitioning the wake and rst pins from logic [1] to logic [0] or forcing the fsi pin to logic [0]. table 6 summarizes the various methods for resetting the device from the latched fail-safe mode. if the fsi pin is tied to gnd, the watchdog fail-safe operation is disabled. loss of v dd if the external 5.0 v supply is not within specification, or even disconnected, all register content is reset. the two outputs can still be driven by the direct inputs in 1:in0. the 33984 uses the battery input to power the output mosfet related current sense circuitry and any other internal logic providing fail-safe device operation with no v dd supplied. in this state, the watchdog, ove r-voltage, over-temperature, and over-current circuitry are fully operational with default values. table 6. fail-safe operation and transitions to other 33984 modes mode fs wake rst wdto comments sleep x 0 0 x device is in sleep mode. all outputs are off. normal 1 x 1 no normal mode. watchdog is active if enabled. fault 0 1 x no the device is currently in fault mode. the faulted output(s) is (are) off. 0 x 1 fail- safe 1 0 1 yes watchdog has timed out and the device is in fail- safe mode. the outputs are as configured with the rfs resistor connected to fsi. rst and wake must be transitioned to logic [0] simultaneously to bring the device out of the fail- safe mode or momentarily tied the fsi pin to ground. 1 1 1 1 1 0 x = don?t care. table 7. output state during fail-safe mode rfs (k ) high side state 0 fail-safe mode disabled 6.0 both hs0 and hs1 off 15 hs0 on, hs1 off 30 both hs0 and hs1 on
analog integrated circuit device data freescale semiconductor 21 33984 functional device operation protection and diagnosis features fault mode the 33984 indicates the following faults as they occur by driving the fs pin to logic [0]: ? over-temperature fault ? open load fault ? over-current fault (high and low) ? over-voltage and under-voltage fault the fs pin will automatically return to logic [1] when the fault condition is removed, exc ept for over-current and in some cases under-voltage. fault information is retained in the fault register and is available (and reset) via the so pin during the first valid spi communication (refer to table 17 ). protection and diagnosis features over-temperature fault (non-latching) the 33984 incorporates over-temperature detection and shutdown circuitry in each output structure. over- temperature detection is enabl ed when an output is in the on state. for the output, an over-temperature fault (otf) condition results in the faulted output tu rning off until the temperature falls below the t sd(hys) . this cycle will continue indefinitely until action is taken by the mcu to shut off the output, or until the offending load is removed. when experiencing this fault, the otf fault bit will be set in the status register and cleare d after either a valid spi read or a power reset of the device. over-voltage fault (non-latching) the 33984 shuts down the out put during an over-voltage fault (ovf) condition on the vpwr pin. the output remains in the off state until the over-v oltage condition is removed. when experiencing this fault, the ovf fault bit is set in the bit od1 and cleared after either a valid spi read or a power reset of the device. the over-voltage protection and diagnostic can be disabled trough the spi (bit ov_dis). under-voltage shutdown (latching or non-latching) the output(s) will latch off at some battery voltage below 6.0 v. as long as the v dd level stays within the normal specified range, the internal l ogic states within the device will be sustained. in the case where battery voltage drops below the under- voltage threshold (vpwruv) output will turn off, fs will go to logic [0], and the fault register uvf bit will be set to 1. two cases need to be considered when the battery level recovers : ? if output(s) command is (are) low, fs will go to logic [1] but the uvf bit will remain set to 1 until the next read operation. ? if the output command is on, then fs will remain at logic [0]. the output must be turned off and on again to re-enable the state of output and release fs . the uvf bit will remain set to 1 until the next read operation. the under-voltage protection can be disabled through the spi (bit uv_dis = 1). in this case, the fs and uvf bits do not report any under-voltage fault condition and the output state will not be changed as long as battery voltage does not drop any lower than 2.5 v. open load fault (non-latching) the 33984 incorporates open load detection circuitry on each output. output open lo ad fault (olf) is detected and reported as a fault condition when that output is disabled (off). the open load fault is detected and latched into the status register after the internal gate voltage is pulled low enough to turn off the output. the olf fault bit is set in the status register. if the open load fault is removed, the status register will be cleared after reading the register. the open load protection can be disabled trough spi (bit ol_dis). it is recommended to disable the open load detection circuitry (ol_dis bit sets to logic [1]) in case of permanent open load fault condition. over-current fault (latching) the device has eight programmable over-current low detection levels (i ocl ) and two programmable over-current high detection levels (i och ) for maximum device protection. the two selectable, simultaneously active over-current detection levels, defined by i och and i ocl , are illustrated in figure 6 . the eight different over-current low detect levels (i ocl0 : i ocl7 ) are likewise illustrated in figure 6 . if the load current level ever reaches the selected over- current low detect level and the over-current condition exceeds the programmed over-current time period (t ocx ), the device will latch the effected output off. if at any time the curr ent reaches the selected i och level, then the device will immediately latch the fault and turn off the output, regardless of the selected t ocl driver. for both cases, the device output will stay off indefinitely until the device is commanded off and then on again. reverse battery the output survives the applicat ion of reverse voltage as low as -16 v. under these conditions, the output?s gates are enhanced to keep the junction temperature less than 150c. the on resistance of the output is fairly similar to that in the normal mode. no additional passive components are required.
analog integrated circuit device data 22 freescale semiconductor 33984 functional device operation ground disconnect protection in the event the 33984 ground is disconnected from load ground, the device protects itself and safely turns off the output regardless the state of the output at the time of disconnection. a 10 k resistor needs to be added between the wake pin and the rest of the circuitry in order to ensure that the device turns off in ca se of ground disconnect, and to prevent this pin from exceeding its maximum ratings table 8. device behavior in case of under-voltage high side switch (vpwr battery voltage) ?? state uv enable in = 0 (falling vpwr) uv enable in = 0 (rising vpwr) uv enable in ??? = 1 (falling vpwr) uv enable in ??? = 1 (rising vpwr) uv disable in = 0 (falling or rising vpwr) uv disable in ??? = 1 (falling or rising vpwr) vpwr > vpwruv output state off off on off off on fs state 1 1 1 0 1 1 spi fault register uvf bit 0 1 until next read 0 1 0 0 vpwruv > vpwr > uvpor output state off off off off off on fs state 0 0 0 0 1 1 spi fault register uvf bit 1 1 1 1 0 0 uvpor > vpwr > 2.5 v ? output state off off off off off on fs state 1 1 1 1 1 1 spi fault register uvf bit 1 until next read 1 1 until next read 1 until next read 0 0 2.5 v > vpwr > 0 v output state off off off off off off fs state 1 1 1 1 1 1 spi fault register uvf bit 1 until next read 1 until next read 1 until next read 1 until next read 0 0 comments uv fault is not latched uv fault is not latched uv fault is latched ? typical value; not guaranteed ?? while vdd remains within specified range. ??? = in is equivalent to in direct input or in_spi spi input.
analog integrated circuit device data freescale semiconductor 23 33984 functional device operation logic commands and registers logic commands and registers spi protocol description the spi interface has a full duplex, three-wire synchronous data transfer with four i/o lines associated with it: serial clock (sclk), serial input (si), serial output (so), and chip select ( cs ). the si / so pins of the 33984 follow a first-in first-out (d7/ d0) protocol with both input and output words transferring the most significant bit (msb) first. all inputs are compatible with 5.0 v cmos logic levels. the spi lines perform the following functions: serial clock (sclk) serial clocks (sclk) the internal shift registers of the 33984 device. the serial input (si) pin accepts data into the input shift register on the falling edge of the sclk signal while the serial output (so) pi n shifts data information out of the so line driver on the rising edge of the sclk signal. it is important that the sc lk pin be in a logic low state whenever cs makes any transition. for this reason, it is recommended that the sclk pin be in a logic [0] state whenever the device is not accessed ( cs logic [1] state). sclk has an active internal pull-down, i dwn . when cs is logic [1], signals at the sclk and si pins are ignor ed and so is tri-stated (high- impedance). see figure 9 and figure 10 . serial input (si) this is a serial interface (si) command data input pin. si instruction is read on the falling edge of sclk. an 8-bit stream of serial data is required on the si pin, starting with d7 to d0. the internal registers of the 33984 are configured and controlled using a 4-bit addressing scheme, as shown in table 9 . register addressing and configuration are described in table 10 . the si input has an active internal pull-down, i dwn . serial output (so) the so data pin is a tri-stateable output from the shift register. the so pin remains in a high-impedance state until the cs pin is put into a logic [0] state. the so data is capable of reporting the status of the output, the device configuration, and the state of the key inputs. the so pin changes states on the rising edge of sclk and reads out on the falling edge of sclk. fault and input status descriptions are provided in table 6 . chip select ( cs ) the cs pin enables communicat ion with the master microcontroller (mcu). when this pin is in a logic [0] state, the device is capable of transferring information to, and receiving information from, the mcu. the 33984 device latches in data from the input shift registers to the addressed registers on the rising edge of cs . the device transfers status information from the power output to the shift register on the falling edge of cs . the so output driver is enabled when cs is logic [0]. cs should transition from a logic [1] to a logic [0] state only when sclk is a logic [0]. cs has an active internal pull-up, i up . figure 9. single 8-bit word spi communication csb si sclk d7 d1 d2 d3 d4 d5 d6 d0 od7 od6 od1 od2 od3 od4 od5 notes: od0 so 1. rstb is in a logic 1 state during the above operation. 2. d0, d1, d2, ..., and d7 relate to the most recent ordered entry of data into the spss 3. od0, od1, od2, ..., and od7 relate to the first 8 bits of ordered fault and status data out of the device. cs so rst 1. rst is a logic [1] state during the above operation. 2. d7:d0 relate to the most recent ordered entry of data into the device. 3. od7:od0 relate to the first 8 bits of ordered fault and status data out of the device. notes
analog integrated circuit device data 24 freescale semiconductor 33984 functional device operation logic commands and registers figure 10. multiple 8-bit word spi communication serial input communication spi communication is accomplished using 8-bit messages. a message is transm itted by the mcu starting with the msb, d7, and ending with the lsb, d0 ( table 9 ). each incoming command message on the si pin can be interpreted using the following bit assignments: the msb (d7) is the watchdog bit and in some cases a register address bit common to both outputs or sp ecific to an output; the next three bits, d6 : d4, are used to select the command register; and the remaining four bits, d3 : d0, are used to configure and control the outputs and th eir protection features. multiple messages can be transmitted in succession to accommodate those applications where daisy chaining is desirable, or to confirm transmitted data, as long as the messages are all multiples of eight bits. any attempt made to latch in a message that is not eight bits will be ignored. the 33984 has defined regist ers, which are used to configure the device and to co ntrol the state of the output. table 10 , summarizes the si regist ers. the registers are addressed via d6 : d4 of the incoming spi word ( table 9 ). csb si sclk d7 d1* d2* d5* d6* d7* d0 d1 d6 d5 d2 d0* od5 od6 od7 d6 d7 od0 od1 od2 d1 d2 d5 figure 4b. multiple 8bit w ord spi com munication notes : d0 so 1. r stb is in a logic 1 state during the above operation. 2 . d 0 , d 1 , d 2 , ..., a n d d 7 re la te to th e m o s t re c e n t o rd e re d e n try o f d a ta in to th e s p s s 3. o d 0, o d 1, o d 2, ..., and o d 7 relate to the first 8 bits of ordered fault and status data out of the device. 4. o d 0, o d 1, o d 2, ..., and o d 7 represent the first 8 bits of ordered fault and status data out of the s pss sclk si so rst cs 1. rst is a logic [1] state during the above operation. 2. d7:d0 relate to the most recent ordered entry of data into the device. 4. od7:od0 relate to the first 8 bits of ordered fault and status data out of the device. notes 3. d7*:d0* relate to the previous 8 bits (last command wo rd) of data that was previously shifted into the device. table 9. si message bit assignment bit sig si msg bit message bit description msb d7 register address bit for output selection. also used for watchdog: toggled to satisfy watchdog requirements. d6 : d4 register address bits. d3 : d1 used to configure the inputs, outputs, and the device protection f eatures and so status content. lsb d0 used to configure the inputs, outputs, and the device protection f eatures and so status content. table 10. serial input address and configuration bit map si register serial input data d7 d6 d5 d4 d3 d2 d1 d0 statr s 0 0 0 0 soa2 soa1 soa0 ocr x 0 0 1 csns1 en in1_spi csns0 en in0_spi sochlr s 0 1 0 sochs socl2s socl1s socl0s cdtolr s 0 1 1 ol_dis s cd_dis s oclt1s oclt0 s dicr s 1 0 0 fast sr s csns high s in dis s a/os osdr 0 1 0 1 0 osd2 osd1 osd0 wdr 1 1 0 1 0 0 wd1 wd0 nar 0 1 1 0 0 0 0 0 uovr 1 1 1 0 0 0 uv_dis ov_dis test x 1 1 1 freescale internal use (test) x = don?t care. s (soa3 bit) = selection of output: logic [0] = hs0, logic [1] = hs1.
analog integrated circuit device data freescale semiconductor 25 33984 functional device operation logic commands and registers device register addressing the following section describes the possible register addresses and their impact on device operation. address x000 ? status register (statr) the statr register is used to read the device status and the various configuration register contents without disrupting the device operation or the regist er contents. the register bits d2:d0, determine the content of th e first eight bits of so data. when register content is specific to one of the two outputs, bit d7 is used to select the desired output (soa3). in addition to the device status, this feature pr ovides the ability to read the content of the ocr, sochl r, cdtolr, dicr, osdr, wdr, nar, and uovr registers. (refer to the section entitled serial output communication (device status return data) .) address x001 ? output control register (ocr) the ocr register allows the mcu to control the outputs through the spi. incoming message bit d0 reflects the desired states of the high si de output hs0 (in0_spi): a logic [1] enables the output switch and a logic [0] turns it off. a logic [1] on message bit d1 enables the current sense (csns) pin. similarly, incoming message bit d2 reflects the desired states of the high side output hs1 (in1_spi): logic [1] enables the output switch and a logic [0] turns it off. a logic [1] on message bit d3 enables the csns pin. in the event that th e current sense is enabled for both outputs, the current will be summed. bit d7 is used to feed the watchdog if enabled. address x010? select over-current high and low register (sochlr) the sochlr register allows the mcu to configure the output over-current low and high detection levels, respectively. each output is independently selected for configuration based on the state of the d7 bit; a write to this register when d7 is logic [0] will configure the current detection levels for the hs0. similarly, if d7 is logic [1] when this register is written, hs1 is configured. each output can be configured to different levels. in addition to protecting the device, this slow blow fuse em ulation feature can be used to optimize the load require ments matching system characteristics. bits d2 : d0 set the over-current low detection level to one of eight possible levels, as shown in table 11 . bit d3 sets the over-current high detection level to one of two levels, which is described in table 12 . address x011 ? current detection time and open load register (cdtolr) the cdtolr register is used by the mcu to determine the amount of time the device will allow an over-current low condition before output latches off occurs. each output is independently selected for confi guration based on the state of the d7 bit. a write to this register when bit 7 is logic [0] will configure the timeout for the hs0. similarly, if d7 is logic [1] when this register is written, then hs1 is configured. bits d1: d0 allow the mcu to select one of four fault blanking times defined in table 13 . note that thes e time-outs apply only to the over-current low detection levels. if the selected over-current high level is reached, the device will latch off within 20 s . a logic [1] on bit d2 disables the over-current low (cd_dis) detection timeout feature. a logic [1] on bit d3 disables the open load (ol) detection feature. table 11. over-current low detection levels socl2 (d2) socl1 (d1) socl0 (d0) over-current low detection (amperes) 0 0 0 25 0 0 1 22.5 0 1 0 20 0 1 1 17.5 1 0 0 15 1 0 1 12.5 1 1 0 10 1 1 1 7.5 table 12. over-current high detection levels soch (d3) over-current high detection (amperes) 0 100 1 75 table 13. over-current low detection blanking time oclt [1:0] timing 00 155 ms 01 10 ms 10 1.2 ms 11 150 s
analog integrated circuit device data 26 freescale semiconductor 33984 functional device operation logic commands and registers address x100 ? direct input control register (dicr) the dicr register is used by the mcu to enable, disable, or configure the direct in pi n control of each output. each output is independently selected for configuration based on the state of bit d7. a write to this register when bit d7 is logic [0] will configure the direct input control for the hs0. similarly, if d7 is logic [1] when this register is written, then hs1 is configured. a logic [0] on bit d1 will enable the output for direct control by the in pin. a logic [1] on bit d1 will disable the output from direct control. while addressing this register, if the input was enabled for direct control, a logic [1] for the d0 bit will result in a boolean and of the in pin with its corresponding d0 message bit when addressing the ocr register. similarly, a logic [0] on the d0 pin results in a boolean or of the in pin with the corresponding message bits when addressing the ocr register. the dicr register is useful if there is a need to independently turn on and off several loads that are pwm?d at the same frequency and duty cycle with only one pwm signal. this type of operation can be accomplished by connecting the pertinent direct in pins of several devices to a pwm output port from the mcu an d configuring each of the outputs to be controlled via their respective direct in pin. the dicr is then used to boolean and the direct in(s) of each of the outputs with the dedicated spi bit that also controls the output. each configured spi bit can now be used to enable and disable the common pwm signal from controlling its assigned output. a logic [1] on bit d2 is used to select the high ratio (c sr1 , 1/41000) on the csns pin fo r the selected output. the default value [0] is used to select the low ratio (c sr0 , 1/20500). a logic [1] on bit d3 is used to select the high speed slew rate for the selected output. the default value [0] corresponds to the low speed slew rate. address 0101 ? output switching delay register (osdr) the osdr register config ures the device with a programmable time delay that is active during output on transitions initiated via the spi (not via direct input). a write to this register config ures both outputs for different delay. whenever the input is commanded to transition from logic [0] to logic [1], both outputs will be held off for the time delay configured in the osdr. the programming of the contents of this register have no effect on device fail-safe mode operation. the default valu e of the osdr register is 000, equating to no delay. this f eature allows the user a way to minimize inrush currents, or surges, thereby allowing loads to be switched on with a single command. there are eight selectable output switching delay times that range from 0ms to 525 ms. refer to table 14 . address 1101 ? watchdog register (wdr) the wdr register is used by the mcu to configure the watchdog timeout. watchdog timeout is configured using bits d1:d0. when d1:d0 bits are programmed for the desired watchdog timeout period, the wd bit (d7) should be toggled as well, ensuring the new timeout period is programmed at the beginning of a new count sequence. refer to table 15 . address 0110 ? no action register (nar) the nar register can be used to no-operation fill spi data packets in a daisy chain spi configuration. this allows devices to not be affected by commands being clocked over a daisy-chained spi configurati on, and by toggling the wd bit (d7), the watchdog circuitry will continue to be reset while no programming or data readback functions are being requested from the device. address 1110 ? under-voltage/over-voltage register (uovr) the uovr register can be used to disable or enable over- voltage and/or under-voltage protection. by default (logic [0]), both protections are active. when disabled, an under-voltage or over-voltage condition fault will not be reported in the output fault register. address x111 ? test the test register is rese rved for test and is not accessible with spi during normal operation. table 14. switching delay osd [2:0] (d2 : d0) turn on delay (ms) hs0 turn on delay (ms) hs1 000 0 0 001 75 0 010 150 150 011 225 150 100 300 300 101 375 300 110 450 450 111 525 450 table 15. watchdog timeout wd [1:0] (d1: d0) timing (ms) 00 620 01 310 10 2500 11 1250
analog integrated circuit device data freescale semiconductor 27 33984 functional device operation logic commands and registers serial output communication (device status return data) when the cs pin is pulled low, the ou tput status register is loaded. meanwhile, the data is clocked out msb- (od7-) first as the new message data is clocked into the si pin. the first eight bits of data clocking out of the so, and following a cs transition, are dependant upon the previously written spi word. any bits clocked out of the so pin after the first eight will be representative of the initial message bits clocked into the si pin since the cs pin first transitioned to a logic [0]. this feature is useful for daisy chaining devices as well as message verification. a valid message length is determined following a cs transition of logic [0] to logic [1]. if there is a valid message length, the data is latched into the appropriate registers. a valid message length is a multiple of eight bits. at this time, the so pin is tri-stated and t he fault status register is now able to accept new fault status information. the output status register corre ctly reflects the status of the statr-selected register data at the time that the cs is pulled to a logic [0] during spi communication and / or for the period of time since the last valid spi communication, with the following exceptions: ? the previous spi communication was determined to be invalid. in this case, the status will be reported as though the invalid spi communication never occurred. ? battery transients below 6.0 v resulting in an under- voltage shutdown of the out puts may result in incorrect data loaded into the status register. the so data transmitted to the mcu during the first spi communication following an under-voltage v pwr condition should be ignored. ?the rst pin transition from a logic [0] to logic [1] while the wake pin is at logic [0] may result in incorrect data loaded into the status regist er. the so data transmitted to the mcu during the first spi communication following this condition should be ignored. serial output bit assignment the 8 bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. table 16 summarizes the so register content. bit od7 reflects the state of the watchdog bit (d7) addressed during the prior comm unication. the value of the previous d7 will determine which output the status information applies to for the fault (fltr), sochlr, cdtolr, and dicr registers. so data will represent information ranging from fault st atus to register contents, user selected by writing to the statr bits d2:d0. note that the so data will continue to reflect the information for each output (depending on the previous d7 state) that was selected during the most recent statr write until changed with an updated statr write. previous address soa[2:0] = 000 if the previous three msbs are 000, bits od6 : od0 will reflect the current state of the fault register (fltr) corresponding to the output previously selected with the bit od7 ( table 17 ). previous address soa[2:0] = 001 data in bits od1:od0 contain csns0 en and in0_spi programmed bits, respectively. data in bits od3:od2 contain csns0 en and in0_spi programmed bits, respectively. previous address soa[2:0] = 010 the data in bit od3 contain the programmed over-current high detection level (refer to table 12 ), and the data in bits od2:od0 contain the programmed over-current low detection levels (refer to table 13 ). table 16. serial output bit map description previous statr d7, d2, d1, d0 serial output returned data soa3 soa2 soa1 soa0 od7 od6 od5 od4 od3 od2 od1 od0 s 0 0 0 s otfs ochfs oclfs olfs uvf ovf fault x 0 0 1 x 0 0 1 csns1 en in1_spi csns0 en in0_spi s 0 1 0 s 0 1 0 sochs socl2s socl1s socl0s s 0 1 1 s 0 1 1 ol_dis s cd_dis s oclt1s oclt0s s 1 0 0 s 1 0 0 fast sr s csns high s in dis s a/o s 0 1 0 1 0 1 0 1 fsm_hs0 osd2 osd1 osd0 1 1 0 1 1 1 0 1 fsm_hs1 wdto wd1 wd0 0 1 1 0 0 1 1 0 in1 pin in0 pin fsi pin wake pin 1 1 1 0 1 1 1 0 ? ? uv_dis ov_dis x 1 1 1 ? ? ? ? see table 1 ? ? ? s = selection of output: logic [0] = hs0, logic [1] = hs1. x = don?t care.
analog integrated circuit device data 28 freescale semiconductor 33984 functional device operation logic commands and registers previous address soa[2:0] = 011 data returned in bits od1 and od0 are current values for the over-current fault blanking time, illustrated in table 13 . bit od2 reports if the over-current detection timeout feature is active. od3 reports if the open load circuitry is active. previous address soa[2:0] =100 the returned data contain the programmed values in the dicr. previous address soa[2:0] = 101 ? soa3 = 0. the returned data contain the programmed values in the osdr. bit od3 (fsm_hs0) reflects the state of the output hs0 in the fail-safe mode after a watchdog timeout occurs. ? soa3 = 1. the returned data contain the programmed values in the wdr. bit od2 (wdto) reflects the status of the watchdog circuitry. if wdto bit is logic [1], the watchdog has timed out and the device is in fail-safe mode. if wdto is logic [0], the device is in normal mode (assuming the device is powered and not in sleep mode), with the watchdog either enabled or disabled. bit od3 (fsm_hs1) reflects the state of the output hs1 in the fail-safe mode after a watchdog timeout occurs. previous address soa[2:0] = 110 ? soa3 = 0. od3:od0 return t he state of the in1, in0, fsi, and wake pins, respectively ( table 18 ). ? soa3 = 1. the returned data contain the programmed values in the uovr. bit od1 reflects the state of the under-voltage protection and bit od0 reflects the state of the over-voltage protection. refer to table 16 ). previous address soa[2:0] =111 null data. no previous register read back command received, so bits od2:od0 are null, or 000. table 17. fault register od7 od6 od5 od4 od3 od2 od1 od0 s otf ochfs oclfs olfs uvf ovf fault od7 (s) = selection of output: logic [0] = hs0, logic [1] = hs1. od6 (otf) = over-temperature flag. od5 (ochfs) = over-current high flag. (this fault is latched.) od4 (oclfs) = over-current low flag. (this fault is latched.) od3 (olfs) = open load flag. od2 (uvf) = under-voltage flag. (this fault is latched or not latched.) od1 (ovf) = over-voltage flag. od0 (fault) = this flag reports a fault and is reset by a read operation. fault report of any fault on hs0 or hs1 note the fs pin reports a fault. for latched faults, this pin is reset by a new switch on command (via spi or direct input in). table 18. pin register od3 od2 od1 od0 in1 pin in0 pin fsi pin wake pin
analog integrated circuit device data freescale semiconductor 29 33984 typical applications typical applications figure 11. typical applications the loads must be chosen in order to guarantee the device normal operating conditions for junction temperatures from - 40 to 150c. in case of permanent short-circuit conditions, the duration and number of acti vation cycles must be limited with a dedicated mcu fault ma nagement, using the fault reporting through the spi. when driving dc motor or solenoid loads demanding multiple switching, an external recirculation device must be used to maintain the device in its safe operating area. two application notes are available: ? an3274, which proposes sa fe configurations of the extreme switch devices in case of application faults, and to protect all circuitry with minimum external components. ? an2469, which provides guidelines for printed circuit board (pcb) design and assembly. development effort will be required by the end users to optimize the board design and pcb layout, in order to reach electromagnetic compatibilit y standards (emission and immunity). output current monitoring this section relates to the output current monitoring for 33984, dual 4.0 m high side switch. this device is a self- protected silicon s witch used to replace electromechanical relays, fuses, and discrete circuits in power management applications. the mc33984 featur es a current recopy which is proportional to the load current. it can be configured between 2 ratios via spi (csr0 and csr1). this section presents the curr ent recopy tolerance of the device and the improvement of this feature with the calibration practice. current recopy tolerance the current sense ratio accuracies described page 9 and 10 (csr0_acc and csr1_acc) take into account: ? part to part deviation due to manufacturing, ? ambient temperature derat ing (from -40 to 125c), ? battery voltage range (from 9 to 16 v). thanks to statistical data analysis performed on 3 production lots (initial testing only), the effect of each contributor has been demonstrated. a/d mcu i/o i/o si so sclk i/o cs si fs vdd fsi csns rst cs in0 sclk wake nc v pwr 33984 100 nf 10 f v dd v dd gnd hs1 hs0 vpwr v pwr 2.5f 10nf load rfsi 1k 2.2k 10k v dd 10 7 8 12 4 2 9 5 13 1 16 6 15 14 3 load voltage regulator v dd v pwr in1 i/o so 11 10 k 10 k 10 k 10 k 10 k 10 k
analog integrated circuit device data 30 freescale semiconductor 33984 typical applications output current monitoring figure 12 shows the csr0 toler ance in function to 3 previous listed contributors in comparison to the minimum and maximum specified values. figure 12. csr0 ratio deviation in function all contributors lower vpwr voltage causes more error. 9.0 v corresponding to the worst case. figure 13 shows the csr0 tolerance without battery variation effect. figure 13. csr0 ratio deviation in function manufacturing and temperature the main contributor is the manufacturing deviation, as described in figure 14 . at 15 a of output current, the tolerance will be about 8.5% versus 10% when all contributors are considered. figure 14. csr0 ratio deviation in function manufacturing part calibration with a calibration strategy, the part to part contribution can be removed. an experiment was done on low output current values (below 5.0 a). the relative csr0 deviation based on only one calibration point per output (5.0 a, vpwr=16 v at 25c) has been performed on 3 production lots. those parts have tested at initial and after hig h temperature operating life test in order to take into account the ageing of devices. table 19 summaries test results covering 99.74% of parts. current recopy at vbat=9v/16v from -40c to 125c 16000 17000 18000 19000 20000 21000 22000 23000 24000 10 15 20 25 output current (a) csns ratio (csr0) spec_max spec_min a verage (data) max(data_9v) at 6 sigmas min(data_9v) at 6 sigmas min(data_16v) at 6 sigmas max(data_16v) at 6 sigmas 10% current recopy at vbat=9v from -40c to 125c 16000 17000 18000 19000 20000 21000 22000 23000 24000 10 15 20 25 output current (a) csns ratio (csr0) table 19. csr0 precision for several output current values with one calibration point at 5.0 a csr0 ratio min max 0.5 a -25% 25% 1.0 a -12% 12% 2.5 a -8.0% 8.0% 5.0 a -5.0% 5.0% current recopy at vbat=9v at 25c 16000 17000 18000 19000 20000 21000 22000 23000 24000 10 15 20 25 output current (a) csns ratio (csr0) spec_max spec_min a verage (data) max(data) at 6 sigmas min(data) at 6 sigmas 8.5%
analog integrated circuit device data freescale semiconductor 31 33984 packaging soldering information packaging soldering information soldering information the 33984 is packaged in a surface mount power package (pqfn), intended to be soldered directly on the printed circuit board. the an2467 provides guidelines for printed circuit board design and assembly.
analog integrated circuit device data 32 freescale semiconductor 33984 packaging package dimensions package dimensions for the most current revision of the package, visit www.freescale.com and perform a keyword search on 98arl10521d. dimensions shown are provided for reference only. fk suffix 16-pin pqfn nonleaded package 98arl10521d issue c
analog integrated circuit device data freescale semiconductor 33 33984 packaging package dimensions (continued) package dimensions (continued) fk suffix 16-pin pqfn nonleaded package 98arl10521d issue c
analog integrated circuit device data 34 freescale semiconductor 33984 additional documentation thermal addendum (rev 3.0) additional documentation thermal addendum (rev 3.0) introduction this thermal addendum is provided as a supplement to the 33984 technical datasheet. the addendum pr ovides thermal performance information that may be critical in the design and development of system appl ications. all electrical, application, and packaging information is provided in the datasheet. packaging and thermal considerations this package is a dual die package. there are two heat sources in the package independently heating with p 1 and p 2 . this results in two junction temperatures, t j1 and t j2 , and a thermal resistance matrix with r ja mn . for m , n = 1, r ja11 is the thermal resistance from junction 1 to the reference temperature while only heat so urce 1 is heating with p 1 . for m = 1, n = 2, r ja12 is the thermal resistance from junction 1 to the reference temperature while heat source 2 is heating with p 2 . this applies to r j21 and r j22 , respectively. the stated values are solely for a thermal performance comparison of one package to another in a standard ized environment. this methodology is not meant to and will not predict the perfor mance of a package in an applic ation-specific environment. stat ed values were obtained by measurement and simula tion according to the standards listed below. standards figure 1. surface mount for power pqfn with exposed pads high side switch 33984 98arl10521d 16-pin pqfn 12 mm x 12 mm note for package dimensions, refer to 98arl10521d. t j1 t j2 = r ja11 r ja21 r ja12 r ja22 . p 1 p 2 table 1. thermal performance comparison thermal resistance 1 = power chip, 2 = logic chip [ c/w] m = 1, n = 1 m = 1, n = 2 m = 2, n = 1 m = 2, n = 2 r ja mn (1) (2) 20 16 39 r jb mn (2) (3) 6.0 2.0 26 r ja mn (1) (4) 53 40 72 r jc mn (5) <0.5 0.0 1.0 notes: 1. per jedec jesd51-2 at natural convection, still air condition. 2. 2s2p thermal test board per jedec jesd51-7 and jesd51-5. 3. per jedec jesd51-8, with the board temperature on the center trace near the power outputs. 4. single layer thermal test board per jedec jesd51-3 and jesd51-5. 5. thermal resistance between the die junction and the exposed pad; ?infinite? heat sink attached to exposed pad. note: recommended via diameter is 0.5 mm. pth (plated through hole) via must be plugged / filled with epoxy or solder mask in order to minimize void formation and to avoid any solder wicking into the via. 1.0 1.0 0.2 0.2 * all measurements are in millimeters
analog integrated circuit device data freescale semiconductor 35 33984 additional documentation thermal addendum (rev 3.0) figure 2. thermal test board device on thermal test board r ja is the thermal resistance between die junction and ambient air. this device is a dual die package. index m indicates the die that is heated. index n refers to the number of the die where the junction temperature is sensed. hs1 hs0 16 15 vpwr 14 gnd 13 16-pin pqfn 0.90 mm pitch 12.0 mm x 12.0 mm body 33984 pin connections a a csns in0 fs fsi cs sclk rst wake si vdd so in1 1 11 10 9 8 7 6 5 4 3 2 12 transparent top view a material: single layer printed circuit board fr4, 1.6 mm thickness cu traces, 0.07 mm thickness outline: 80 mm x 100 mm board area, including edge connector for thermal testing area a: cu heat-spreading areas on board surface ambient conditions: natural convection, still air table 2. thermal resistance performance thermal resistance area a (mm 2 ) 1 = power chip, 2 = logic chip ( c/w) m = 1, n = 1 m = 1, n = 2 m = 2, n = 1 m = 2, n = 2 r ja mn 055 42 74 300 41 31 66 600 38 29 64
analog integrated circuit device data 36 freescale semiconductor 33984 additional documentation thermal addendum (rev 3.0) figure 3. device on thermal test board r ja figure 4. transient thermal resistance r ja (1 w step response) device on thermal test board area a = 600(mm 2 ) 0 10 20 30 40 50 60 70 80 heat spreading area a [mm2] thermal resistance [oc/w ] 0300 600 r ja11 r ja22 r ja12 =r ja21 x 0.1 1 10 100 1.00e-03 1.00e-02 1.00e-01 1.00e+00 1.00e+01 1.00e+02 1.00e+03 1.00e+04 tim e[s ] thermal resistance [oc/w] r ja11 r ja22 r ja12 =r ja21 x
analog integrated circuit device data freescale semiconductor 37 33984 revision history revision history revision date description of changes 6.0 2/2006 ? implemented revision history page ? deletion of mc33984 part number, replaced with mc33984b. 7.0 5/2006 ? corrected pin connections to the proper case outline ? added final sentence to open load fault (non-latching) ? corrected heading labels on input timing switching characteristics ? changed labels in the typical applications drawing ? corrected package dimensions to revision c ? added thermal addendum (rev 3.0) . 8.0 1/2007 ? added rohs logo 9.0 1/2007 ? changed several names on the typical applications on page 29 ? added section output current monitoring on page 29 10.0 8/2007 ? updated freescale format and style ? updated thermal rating (r ja ) junction-to-ambient (from 20 to 30 c/w) ? changes label for hs1 switching delay time (osd[2:0]) and hs0 switching delay time (osd[2:0]) ? added functional internal block description ? updated device behavior in case of under-voltage 11.0 10/2009 ? added mc33984c to the ordering information ? added a device variation table 12.0 4/2010 ? corrected link from device variation table to table 3. no technical changes. 13.0 6/2010 ? corrected typo in tables 16 and 17 (faults to f ault) and added ?fault report of any fault on hs0 or hs1? to table 17. 14.0 5/2012 ? removed mc33984bpna ? updated orderable part number from mc33984cpna to MC33984CHFK ? updated (6) ? updated soldering information ? updated freescale form and style
document number: mc33984 rev. 14.0 5/2012 information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fa bricate any integrated circuits on the information in this document. freescale reserves the right to make chang es without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particul ar purpose, nor does freescale assume any liability arising out of the application or us e of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or specifications can and do vary in differ ent applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s te chnical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.reg.net/v2/webservices/freescale/docs/termsandconditions.htm freescale, the freescale logo, altivec, c-5, codetest, codewarrior, coldfire, c-ware, energy efficient solutions logo, mobilegt, powerquicc, qoriq, qorivva, starcore, and symphony are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. airfast, beekit, beestack, coldfire+, co renet, flexis, magniv, mxc, platform in a package, processor expert, qoriq qonverge, quicc engine, ready play, smartmos, turbolink, vybrid, and xtrinsic are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2012 freescale semiconductor, inc. how to reach us: home page: freescale.com web support: freescale.com/support

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